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Single Stuck Line is a fault model used in digital circuits. It is used for post manufacturing testing, not design testing. The model assumes that one line or node in the digital circuit is stuck at logic high or logic low. When a line is stuck it is called a fault.

Digital circuits can be divided into :-

1) Gate level or combinational circuits which contain no storage (latches and/or flip flops) but only gates like NAND, OR, XOR, etc.

2) Sequential circuits which contain storage.

This fault model applies to gate level circuits, or a block of a sequential circuit which can be separated from the storage elements. Ideally a gate-level circuit would be completely tested by applying all possible inputs and checking that they gave the right outputs, but this is completely impractical: an adder to add two 32-bit numbers would require 2^64 = 1.8*10^19 tests, taking 58 years at 1 ns/test.

The stuck at fault model assumes that only one input on one gate will be faulty at a time, assuming that if more are faulty, a test that can detect any single fault, should easily find multiple faults.

To use this fault model, each input pin on each gate in turn, is assumed to be grounded, and a test vector is developed to indicate the circuit is faulty.

Here a test vector is a collection of bits to apply to the circuit's inputs, and a collection of bits expected at the circuit's output. If the gate pin under consideration is grounded, and this test vector applied to the circuit, at least one of the output bits will not agree with that in the test vector. After obtaining the test vectors for grounded pins, each pin in turn is connected to a logic one and another set of test vector is developed to find these faults.

Each of these faults is called a single stuck-at-0 or a single stuck-at-1 fault respectively.

This model worked well for transistor-transistor logic (TTL), which was the logic of choice during the '70s and '80s. So well that manufacturers advertised how well they tested their circuits by a number called stuck-at fault coverage, which was the percentage of all possible stuck-at faults that their testing process would find.

It also works moderately well for CMOS, unfortunately not all CMOS faults can be modeled by a stuck at model. CMOS has what is called a stuck-open fault which cannot be reliably tested with one test vector, and requires two to be applied sequentially. The model doesn't include bridging faults between adjacent signal lines, occurring e.g. in bus connections and array structures, as well. Nevertheless the concept of single stuck-at faults is widely used, and with some additional tests, has allowed industry to ship an acceptable low number of bad circuits.

The testing based on this model is aided by several things :-

1) A test developed for a single stuck at fault often finds a large number of other stuck at faults.

2) A series of tests for stuck at faults will often, purely by serendipity, find a large number of other faults, like the stuck-open faults. This is sometimes called "windfall" fault coverage.

3) Another type of testing called IDDQ testing measures the way the power supply current of a CMOS integrated circuit changes, when a small number of slowly changing test vectors are applied. Since CMOS draws a very low current when its inputs are static, any increase in that current indicates a potential problem.

A fault model is an engineering model of something that could go wrong in the construction or operation of a piece of equipment. From the model, the designer or user can then predict the consequences of this particular fault. Fault models can be used in almost all branches of engineering.

A signal, or gate output, is stuck at a 0 or 1 value, independent of the inputs to the circuit.

A stuck-at fault is a particular fault model used by fault simulators and automatic test pattern generation (ATPG) tools to mimic a manufacturing defect within an integrated circuit. Individual signals and pins are assumed to be stuck at Logical '1', '0' and 'X'. 

For example, an output is tied to a logical 1 state during test generation to assure that a manufacturing defect with that type of behavior can be found with a specific test pattern. Likewise the output could be tied to a logical 0 to model the behavior of a defective circuit that cannot switch its output pin.

Not all faults can be analyzed using the stuck-at fault model. Compensation for static hazards, namely branching signals, can render a circuit untestable using this model.

Two signals are connected together when they should not be. Depending on the logic circuitry employed, this may result in a wired-OR or wired-AND logic function. Since there are O(n^2) potential bridging faults, they are normally restricted to signals that are physically adjacent in the design.

Here a wire is assumed broken, and one or more inputs are disconnected from the output that should drive them. As with bridging faults, the resulting behavior depends on the circuit implementation.

The signal eventually assumes the correct value, but more slowly (or rarely, more quickly) than normal.

Hi guys, myself Anand P .I am doing a professional degree course in Electronics and Communication. I have been into making electronics projects for some time now and I wanted to share some of my knowledge about simpler projects that I have tried and worked out. I have been collecting information about different electronics projects that can be well tried out if you have some basic knowledge in this field. Don't worry if you haven't had any previous experience in making circuits. I can always help you out. Many of my friends have asked me why don't I start a new blog exclusively to share my knowledge in this field. But as always I don't think I can manage another blog exclusively for that. I will be making posts about the projects that I have tried before and worked out well enough and I will continue making posts about some of the newer projects as and when I work it out. I would like you all to reply after trying out the circuit. I do welcome suggestions and doubts too.

The operation of the circuit is based on superheterodyning principle which is commonly used in superheterodyne receivers. The circuit utilizes two RF oscillators. The frequencies of both oscillators are fixed at 5.5 MHz. The first RF oscillator comprises transistor T1 (BF 494) and a 5.5MHz ceramic filter commonly used in TV sound-IF section. The second oscillator is a Colpitt’s oscillator realised with the help of transistor T3 (BF494) and inductor L1 (whose construction details follow) shunted by trimmer capacitor VC1. These two oscillators’ frequencies (say Fx and Fy) are mixed in the mixer transistor T2 (another BF 494) and the difference or the beat frequency (Fx - Fy) output from collector of transistor T2 is connected to detector stage comprising diodes D1 and D2 (both OA 79). The output is a pulsating DC which is passed through a low-pass filter realised with the help of a 10k resistor R12 and two 15nF capacitors C6 and C10. It is then passed to AF amplifier IC1 (2822M) via volume control VR1 and the output is fed to an 8-ohm/1W speaker. The inductor L1 can be constructed using 15 turns of 25SWG wire on a 10cm (4-inch) diameter air-core former and then cementing it with insulating varnish. For proper operation of the circuit it is critical that frequencies of both the oscillators are the same so as to obtain zero beat in the absence of any metal in the near vicinity of the circuit. The alignment of oscillator 2 (to match oscillator 1 frequency) can be done with the help of trimmer capacitor VC1. When the two frequencies are equal, the beat frequency is zero, i.e. beat frquency = Fx - Fy = 0, and thus there is no sound from the loudspeaker. When search coil L1 passes over metal, the metal changes its inductance, thereby changing the second oscillator’s frequency. So now Fx - Fy is not zero and the loudspeaker sounds. Thus one is able to detect presence of metal.

From my results, the metal detector circuit that I have shown above have the longest range (I am talking about non-commercial ones). It can detect up to 10 to 15 centimeters. It can detect iron nails or coins hid under soil or sand very efficiently. The sound produced is high when the metal is near to the surface. Its sensitivity decreases as the metal is deeper. Try it out with different type of soils, you will see that its sensitivity is higher if soil is more sandy and sensitivity is lower if soil has more iron content. With this metal detector, you can very easily find out lost coins in the beach. Try it out yourself and reply with your results. Don't hesitate to clear your doubts before setting up the circuit.